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Annotation of OpenXM_contrib/gmp/mpn/alpha/rshift.asm, Revision 1.1.1.1

1.1       maekawa     1: dnl  Alpha mpn_rshift -- Shift a number right.
                      2:
                      3: dnl  Copyright (C) 1994, 1995, 2000 Free Software Foundation, Inc.
                      4:
                      5: dnl  This file is part of the GNU MP Library.
                      6:
                      7: dnl  The GNU MP Library is free software; you can redistribute it and/or modify
                      8: dnl  it under the terms of the GNU Lesser General Public License as published by
                      9: dnl  the Free Software Foundation; either version 2.1 of the License, or (at your
                     10: dnl  option) any later version.
                     11:
                     12: dnl  The GNU MP Library is distributed in the hope that it will be useful, but
                     13: dnl  WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
                     14: dnl  or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU Lesser General Public
                     15: dnl  License for more details.
                     16:
                     17: dnl  You should have received a copy of the GNU Lesser General Public License
                     18: dnl  along with the GNU MP Library; see the file COPYING.LIB.  If not, write to
                     19: dnl  the Free Software Foundation, Inc., 59 Temple Place - Suite 330, Boston,
                     20: dnl  MA 02111-1307, USA.
                     21:
                     22: include(`../config.m4')
                     23:
                     24: dnl  INPUT PARAMETERS
                     25: dnl  res_ptr   r16
                     26: dnl  s1_ptr    r17
                     27: dnl  size      r18
                     28: dnl  cnt       r19
                     29:
                     30: dnl  This code runs at 4.8 cycles/limb on the 21064.  With infinite unrolling,
                     31: dnl  it would take 4 cycles/limb.  It should be possible to get down to 3
                     32: dnl  cycles/limb since both ldq and stq can be paired with the other used
                     33: dnl  instructions.  But there are many restrictions in the 21064 pipeline that
                     34: dnl  makes it hard, if not impossible, to get down to 3 cycles/limb:
                     35:
                     36: dnl  1. ldq has a 3 cycle delay, srl and sll have a 2 cycle delay.
                     37: dnl  2. Only aligned instruction pairs can be paired.
                     38: dnl  3. The store buffer or silo might not be able to deal with the bandwidth.
                     39:
                     40: ASM_START()
                     41: PROLOGUE(mpn_rshift)
                     42:        ldq     r4,0(r17)       C load first limb
                     43:        addq    r17,8,r17
                     44:        subq    r31,r19,r7
                     45:        subq    r18,1,r18
                     46:        and     r18,4-1,r20     C number of limbs in first loop
                     47:        sll     r4,r7,r0        C compute function result
                     48:
                     49:        beq     r20,$L0
                     50:        subq    r18,r20,r18
                     51:
                     52:        ALIGN(8)
                     53: $Loop0:
                     54:        ldq     r3,0(r17)
                     55:        addq    r16,8,r16
                     56:        addq    r17,8,r17
                     57:        subq    r20,1,r20
                     58:        srl     r4,r19,r5
                     59:        sll     r3,r7,r6
                     60:        bis     r3,r3,r4
                     61:        bis     r5,r6,r8
                     62:        stq     r8,-8(r16)
                     63:        bne     r20,$Loop0
                     64:
                     65: $L0:   beq     r18,$Lend
                     66:
                     67:        ALIGN(8)
                     68: $Loop: ldq     r3,0(r17)
                     69:        addq    r16,32,r16
                     70:        subq    r18,4,r18
                     71:        srl     r4,r19,r5
                     72:        sll     r3,r7,r6
                     73:
                     74:        ldq     r4,8(r17)
                     75:        srl     r3,r19,r1
                     76:        bis     r5,r6,r8
                     77:        stq     r8,-32(r16)
                     78:        sll     r4,r7,r2
                     79:
                     80:        ldq     r3,16(r17)
                     81:        srl     r4,r19,r5
                     82:        bis     r1,r2,r8
                     83:        stq     r8,-24(r16)
                     84:        sll     r3,r7,r6
                     85:
                     86:        ldq     r4,24(r17)
                     87:        srl     r3,r19,r1
                     88:        bis     r5,r6,r8
                     89:        stq     r8,-16(r16)
                     90:        sll     r4,r7,r2
                     91:
                     92:        addq    r17,32,r17
                     93:        bis     r1,r2,r8
                     94:        stq     r8,-8(r16)
                     95:
                     96:        bgt     r18,$Loop
                     97:
                     98: $Lend: srl     r4,r19,r8
                     99:        stq     r8,0(r16)
                    100:        ret     r31,(r26),1
                    101: EPILOGUE(mpn_rshift)
                    102: ASM_END()