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version 1.1.1.1, 2000/01/10 15:35:25 version 1.1.1.2, 2003/08/25 16:06:26
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   Copyright 1996, 2001 Free Software Foundation, Inc.
   
   This file is part of the GNU MP Library.
   
   The GNU MP Library is free software; you can redistribute it and/or modify
   it under the terms of the GNU Lesser General Public License as published by
   the Free Software Foundation; either version 2.1 of the License, or (at your
   option) any later version.
   
   The GNU MP Library is distributed in the hope that it will be useful, but
   WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
   or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU Lesser General Public
   License for more details.
   
   You should have received a copy of the GNU Lesser General Public License
   along with the GNU MP Library; see the file COPYING.LIB.  If not, write to
   the Free Software Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA
   02111-1307, USA.
   
   
   
   
   
 This directory contains mpn functions for various SPARC chips.  Code that  This directory contains mpn functions for various SPARC chips.  Code that
 runs only on version 8 SPARC implementations, is in the v8 subdirectory.  runs only on version 8 SPARC implementations, is in the v8 subdirectory.
   
Line 8  RELEVANT OPTIMIZATION ISSUES
Line 31  RELEVANT OPTIMIZATION ISSUES
 On most early SPARC implementations, the ST instructions takes multiple  On most early SPARC implementations, the ST instructions takes multiple
 cycles, while a STD takes just a single cycle more than an ST.  For the CPUs  cycles, while a STD takes just a single cycle more than an ST.  For the CPUs
 in SPARCstation I and II, the times are 3 and 4 cycles, respectively.  in SPARCstation I and II, the times are 3 and 4 cycles, respectively.
 Therefore, combining two ST instrucitons into a STD when possible is a  Therefore, combining two ST instructions into a STD when possible is a
 significant optimiation.  significant optimization.
   
 Later SPARC implementations have single cycle ST.  Later SPARC implementations have single cycle ST.
   
Line 19  programs that perform so many memory operations that t
Line 42  programs that perform so many memory operations that t
 non-memory operations to issue in parallel with all memory operations, using  non-memory operations to issue in parallel with all memory operations, using
 LDD and STD when possible helps.  LDD and STD when possible helps.
   
   UltraSPARC-1/2 has very slow integer multiplication.  In the v9 subdirectory,
   we therefore use floating-point multiplication.
   
 STATUS  STATUS
   
 1. On a SuperSPARC, mpn_lshift and mpn_rshift run at 3 cycles/limb, or 2.5  1. On a SuperSPARC, mpn_lshift and mpn_rshift run at 3 cycles/limb, or 2.5
Line 31  STATUS
Line 57  STATUS
 3. mpn_mul_1 runs at what is believed to be optimal speed.  3. mpn_mul_1 runs at what is believed to be optimal speed.
   
 4. On SuperSPARC, mpn_addmul_1 and mpn_submul_1 could both be improved by a  4. On SuperSPARC, mpn_addmul_1 and mpn_submul_1 could both be improved by a
    cycle by avoiding one of the add instrucitons.  See a29k/addmul_1.     cycle by avoiding one of the add instructions.  See a29k/addmul_1.
   
 The speed of the code for other SPARC implementations is uncertain.  The speed of the code for other SPARC implementations is uncertain.

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