version 1.1.1.1, 2000/01/10 15:35:26 |
version 1.1.1.3, 2003/08/25 16:06:29 |
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This directory contains mpn functions optimized for Intel Pentium |
Copyright 1996, 1999, 2000, 2001 Free Software Foundation, Inc. |
processors. |
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RELEVANT OPTIMIZATION ISSUES |
This file is part of the GNU MP Library. |
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1. Pentium doesn't allocate cache lines on writes, unlike most other modern |
The GNU MP Library is free software; you can redistribute it and/or modify |
processors. Since the functions in the mpn class do array writes, we have to |
it under the terms of the GNU Lesser General Public License as published by |
handle allocating the destination cache lines by reading a word from it in the |
the Free Software Foundation; either version 2.1 of the License, or (at your |
loops, to achieve the best performance. |
option) any later version. |
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2. Pairing of memory operations requires that the two issued operations refer |
The GNU MP Library is distributed in the hope that it will be useful, but |
to different cache banks. The simplest way to insure this is to read/write |
WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY |
two words from the same object. If we make operations on different objects, |
or FITNESS FOR A PARTICULAR PURPOSE. See the GNU Lesser General Public |
they might or might not be to the same cache bank. |
License for more details. |
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You should have received a copy of the GNU Lesser General Public License |
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along with the GNU MP Library; see the file COPYING.LIB. If not, write to |
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the Free Software Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA |
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02111-1307, USA. |
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INTEL PENTIUM P5 MPN SUBROUTINES |
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This directory contains mpn functions optimized for Intel Pentium (P5,P54) |
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processors. The mmx subdirectory has additional code for Pentium with MMX |
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(P55). |
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STATUS |
STATUS |
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1. mpn_lshift and mpn_rshift run at about 6 cycles/limb, but the Pentium |
cycles/limb |
documentation indicates that they should take only 43/8 = 5.375 cycles/limb, |
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or 5 cycles/limb asymptotically. |
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2. mpn_add_n and mpn_sub_n run at asymptotically 2 cycles/limb. Due to loop |
mpn_add_n/sub_n 2.375 |
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mpn_mul_1 12.0 |
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mpn_add/submul_1 14.0 |
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mpn_mul_basecase 14.2 cycles/crossproduct (approx) |
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mpn_sqr_basecase 8 cycles/crossproduct (approx) |
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or 15.5 cycles/triangleproduct (approx) |
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mpn_l/rshift 5.375 normal (6.0 on P54) |
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1.875 special shift by 1 bit |
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mpn_divrem_1 44.0 |
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mpn_mod_1 28.0 |
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mpn_divexact_by3 15.0 |
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mpn_copyi/copyd 1.0 |
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Pentium MMX gets the following improvements |
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mpn_l/rshift 1.75 |
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1. mpn_add_n and mpn_sub_n run at asymptotically 2 cycles/limb. Due to loop |
overhead and other delays (cache refill?), they run at or near 2.5 cycles/limb. |
overhead and other delays (cache refill?), they run at or near 2.5 cycles/limb. |
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3. mpn_mul_1, mpn_addmul_1, mpn_submul_1 all run 1 cycle faster than they |
1. mpn_mul_1, mpn_addmul_1, mpn_submul_1 all run 1 cycle faster than they |
should... |
should. Intel documentation says a mul instruction is 10 cycles, but it |
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measures 9 and the routines using it run as 9. |
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P55 MMX AND X87 |
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The cost of switching between MMX and x87 floating point on P55 is about 100 |
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cycles (fld1/por/emms for instance). In order to avoid that the two aren't |
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mixed and currently that means using MMX and not x87. |
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MMX offers a big speedup for lshift and rshift, and a nice speedup for |
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16-bit multipliers in mul_1. If fast code using x87 is found then perhaps |
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the preference for MMX will be reversed. |
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P54 SHLDL |
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mpn_lshift and mpn_rshift run at about 6 cycles/limb on P5 and P54, but the |
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documentation indicates that they should take only 43/8 = 5.375 cycles/limb, |
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or 5 cycles/limb asymptotically. The P55 runs them at the expected speed. |
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It seems that on P54 a shldl or shrdl allows pairing in one following cycle, |
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but not two. For example, back to back repetitions of the following |
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shldl( %cl, %eax, %ebx) |
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xorl %edx, %edx |
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xorl %esi, %esi |
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run at 5 cycles, as expected, but repetitions of the following run at 7 |
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cycles, whereas 6 would be expected (and is achieved on P55), |
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shldl( %cl, %eax, %ebx) |
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xorl %edx, %edx |
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xorl %esi, %esi |
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xorl %edi, %edi |
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xorl %ebp, %ebp |
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Three xorls run at 7 cycles too, so it doesn't seem to be pairing inhibited |
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only in the second following cycle. |
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Avoiding this problem would bring P54 shifts down from 6.0 c/l to 5.5 with a |
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pattern of shift, 2 loads, shift, 2 stores, shift, etc. A start has been |
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made on something like that, but it's not yet complete. |
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OTHER NOTES |
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Prefetching Destinations |
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Pentium doesn't allocate cache lines on writes, unlike most other modern |
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processors. Since the functions in the mpn class do array writes, we |
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have to handle allocating the destination cache lines by reading a word |
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from it in the loops, to achieve the best performance. |
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Prefetching Sources |
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Prefetching of sources is pointless since there's no out-of-order loads. |
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Any load instruction blocks until the line is brought to L1, so it may |
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as well be the load that wants the data which blocks. |
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Data Cache Bank Clashes |
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Pairing of memory operations requires that the two issued operations |
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refer to different cache banks (ie. different addresses modulo 32 |
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bytes). The simplest way to ensure this is to read/write two words from |
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the same object. If we make operations on different objects, they might |
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or might not be to the same cache bank. |
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PIC %eip Fetching |
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A simple call $+5 and popl can be used to get %eip, there's no need to |
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balance calls and returns since P5 doesn't have any return stack branch |
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prediction. |
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Float Multiplies |
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fmul is pairable and can be issued every 2 cycles (with a 4 cycle |
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latency for data ready to use). This is a lot better than integer mull |
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or imull at 9 cycles non-pairing. Unfortunately the advantage is |
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quickly eaten away by needing to throw data through memory back to the |
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integer registers to adjust for fild and fist being signed, and to do |
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things like propagating carry bits. |
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REFERENCES |
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"Intel Architecture Optimization Manual", 1997, order number 242816. This |
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is mostly about P5, the parts about P6 aren't relevant. Available on-line: |
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http://download.intel.com/design/PentiumII/manuals/242816.htm |
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---------------- |
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Local variables: |
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mode: text |
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fill-column: 76 |
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End: |