Annotation of OpenXM_contrib2/asir2000/include/inline.h, Revision 1.7
1.3 noro 1: /*
2: * Copyright (c) 1994-2000 FUJITSU LABORATORIES LIMITED
3: * All rights reserved.
4: *
5: * FUJITSU LABORATORIES LIMITED ("FLL") hereby grants you a limited,
6: * non-exclusive and royalty-free license to use, copy, modify and
7: * redistribute, solely for non-commercial and non-profit purposes, the
8: * computer program, "Risa/Asir" ("SOFTWARE"), subject to the terms and
9: * conditions of this Agreement. For the avoidance of doubt, you acquire
10: * only a limited right to use the SOFTWARE hereunder, and FLL or any
11: * third party developer retains all rights, including but not limited to
12: * copyrights, in and to the SOFTWARE.
13: *
14: * (1) FLL does not grant you a license in any way for commercial
15: * purposes. You may use the SOFTWARE only for non-commercial and
16: * non-profit purposes only, such as academic, research and internal
17: * business use.
18: * (2) The SOFTWARE is protected by the Copyright Law of Japan and
19: * international copyright treaties. If you make copies of the SOFTWARE,
20: * with or without modification, as permitted hereunder, you shall affix
21: * to all such copies of the SOFTWARE the above copyright notice.
22: * (3) An explicit reference to this SOFTWARE and its copyright owner
23: * shall be made on your publication or presentation in any form of the
24: * results obtained by use of the SOFTWARE.
25: * (4) In the event that you modify the SOFTWARE, you shall notify FLL by
1.4 noro 26: * e-mail at risa-admin@sec.flab.fujitsu.co.jp of the detailed specification
1.3 noro 27: * for such modification or the source code of the modified part of the
28: * SOFTWARE.
29: *
30: * THE SOFTWARE IS PROVIDED AS IS WITHOUT ANY WARRANTY OF ANY KIND. FLL
31: * MAKES ABSOLUTELY NO WARRANTIES, EXPRESSED, IMPLIED OR STATUTORY, AND
32: * EXPRESSLY DISCLAIMS ANY IMPLIED WARRANTY OF MERCHANTABILITY, FITNESS
33: * FOR A PARTICULAR PURPOSE OR NONINFRINGEMENT OF THIRD PARTIES'
34: * RIGHTS. NO FLL DEALER, AGENT, EMPLOYEES IS AUTHORIZED TO MAKE ANY
35: * MODIFICATIONS, EXTENSIONS, OR ADDITIONS TO THIS WARRANTY.
36: * UNDER NO CIRCUMSTANCES AND UNDER NO LEGAL THEORY, TORT, CONTRACT,
37: * OR OTHERWISE, SHALL FLL BE LIABLE TO YOU OR ANY OTHER PERSON FOR ANY
38: * DIRECT, INDIRECT, SPECIAL, INCIDENTAL, PUNITIVE OR CONSEQUENTIAL
39: * DAMAGES OF ANY CHARACTER, INCLUDING, WITHOUT LIMITATION, DAMAGES
40: * ARISING OUT OF OR RELATING TO THE SOFTWARE OR THIS AGREEMENT, DAMAGES
41: * FOR LOSS OF GOODWILL, WORK STOPPAGE, OR LOSS OF DATA, OR FOR ANY
42: * DAMAGES, EVEN IF FLL SHALL HAVE BEEN INFORMED OF THE POSSIBILITY OF
43: * SUCH DAMAGES, OR FOR ANY CLAIM BY ANY OTHER PARTY. EVEN IF A PART
44: * OF THE SOFTWARE HAS BEEN DEVELOPED BY A THIRD PARTY, THE THIRD PARTY
45: * DEVELOPER SHALL HAVE NO LIABILITY IN CONNECTION WITH THE USE,
46: * PERFORMANCE OR NON-PERFORMANCE OF THE SOFTWARE.
47: *
1.7 ! noro 48: * $OpenXM: OpenXM_contrib2/asir2000/include/inline.h,v 1.6 2001/08/24 07:42:44 noro Exp $
1.3 noro 49: */
1.1 noro 50: #define DMB(base,a1,a2,u,l) (l)=dmb(base,a1,a2,&(u));
51: #define DMAB(base,a1,a2,a3,u,l) (l)=dmab(base,a1,a2,a3,&(u));
52: #define DMAR(a1,a2,a3,d,r) (r)=dmar(a1,a2,a3,d);
1.7 ! noro 53: /* XXX special macro for X86 */
! 54: #define DMA0(a1,a2,a3,u,l) DMA(a1,a2,a3,u,l)
1.1 noro 55:
56: #define DM27(a1,a2,u,l) (l)=dm_27(a1,a2,&(u));
57: #define DMA27(a1,a2,a3,u,l) (l)=dma_27(a1,a2,a3,&(u));
58: #define DSAB27(base,a1,a2,u,l) (l)=dmab(base,a1,BASE27,a2,&(u));
59:
1.6 noro 60: #if defined(__GNUC__) || defined(__alpha) || defined(mips) || defined(_IBMR2)
1.1 noro 61: #define DM(a1,a2,u,l)\
62: {UL _t;\
63: _t=(UL)(a1)*(UL)(a2);\
64: (u)=(unsigned int)(_t>>BSH);\
65: (l)=(unsigned int)(_t&BMASK);}
66:
67: #define DMA(a1,a2,a3,u,l)\
68: {UL _t;\
69: _t=(UL)(a1)*(UL)(a2)+(UL)(a3);\
70: (u)=(unsigned int)(_t>>BSH);\
71: (l)=(unsigned int)(_t&BMASK);}
72:
73: #define DMA2(a1,a2,a3,a4,u,l)\
74: {UL _t;\
75: _t=(UL)(a1)*(UL)(a2)+(UL)(a3)+(UL)(a4);\
76: (u)=(unsigned int)(_t>>BSH);\
77: (l)=(unsigned int)(_t&BMASK);}
78:
79: #define DSAB(base,a1,a2,u,l)\
80: {UL _t;\
81: _t=(((UL)(a1))<<BSH)|((UL)(a2));\
82: (u)=(unsigned int)(_t/((UL)(base)));\
1.2 noro 83: (l)=(unsigned int)(_t-((UL)(base)*(UL)(u)));}
1.1 noro 84: #else
85: #define DM(a1,a2,u,l) (l)=dm(a1,a2,&(u));
86: #define DMA(a1,a2,a3,u,l) (l)=dma(a1,a2,a3,&(u));
87: #define DMA2(a1,a2,a3,a4,u,l) (l)=dma2(a1,a2,a3,a4,&(u));
88: #define DSAB(base,a1,a2,u,l) (l)=dsab(base,a1,a2,&(u));
89: #endif
90:
91: #define DQR(a,b,q,r)\
92: (q)=(a)/(b);\
93: (r)=(a)-(b)*(q);
94:
95: #if defined(sparc)
96: #undef DSAB
97: #undef DSAB27
98:
99: #define DSAB(base,a1,a2,u,l)\
100: {unsigned int _t;\
101: asm volatile("wr %0,%%g0,%%y" : : "r"(a1) );\
102: asm volatile("udiv %1,%2,%0" :"=r"(_t): "r"(a2),"r"(base) );\
103: (l)=(unsigned int)(a2)-(unsigned int)(_t)*(unsigned int)(base);\
104: (u)=(_t);}
105:
106: #define DSAB27(base,a1,a2,u,l) (l)=dsab_27(base,a1,a2,&(u));
107: #endif
108:
109: #if defined(VISUAL)
110:
111: #undef DM
112: #undef DMA
113: #undef DMA2
114: #undef DMB
115: #undef DMAB
116: #undef DMAR
117: #undef DSAB
118: #undef DM27
119: #undef DMA27
120: #undef DSAB27
121:
122: #define DSAB(base,a1,a2,u,l)\
123: {\
124: unsigned int _t1,_t2,_d;\
125: _t1=a1;_t2=a2;_d=base;\
126: __asm\
127: {\
128: __asm mov edx,_t1\
129: __asm mov eax,_t2\
130: __asm div _d\
131: __asm mov _t1,eax\
132: __asm mov _t2,edx\
133: }\
134: u=_t1;l=_t2;\
135: }
136:
137: #define DM(a1,a2,u,l)\
138: {\
139: unsigned int _t1,_t2;\
140: _t1=a1;_t2=a2;\
141: __asm\
142: {\
143: __asm mov eax,_t1\
144: __asm mul _t2\
145: __asm mov _t1,edx\
146: __asm mov _t2,eax\
147: }\
148: u=_t1;l=_t2;\
149: }
150:
151: #define DMA(a1,a2,a3,u,l)\
152: {\
153: unsigned int _t1,_t2,_t3;\
154: _t1=a1;_t2=a2;_t3=a3;\
155: __asm\
156: {\
157: __asm mov eax,_t1\
158: __asm mul _t2\
159: __asm add eax,_t3\
160: __asm adc edx,0\
161: __asm mov _t1,edx\
162: __asm mov _t2,eax\
163: }\
164: u=_t1;l=_t2;\
165: }
166:
167: #define DMA2(a1,a2,a3,a4,u,l)\
168: {\
169: unsigned int _t1,_t2,_t3,_t4;\
170: _t1=a1;_t2=a2;_t3=a3;_t4=a4;\
171: __asm\
172: {\
173: __asm mov eax,_t1\
174: __asm mul _t2\
175: __asm add eax,_t3\
176: __asm adc edx,0\
177: __asm add eax,_t4\
178: __asm adc edx,0\
179: __asm mov _t1,edx\
180: __asm mov _t2,eax\
181: }\
182: u=_t1;l=_t2;\
183: }
184:
185: #define DMB(base,a1,a2,u,l)\
186: {\
187: unsigned int _t1,_t2,_d;\
188: _t1=a1;_t2=a2;_d=base;\
189: __asm\
190: {\
191: __asm mov eax,_t1\
192: __asm mul _t2\
193: __asm div _d\
194: __asm mov _t1,eax\
195: __asm mov _t2,edx\
196: }\
197: u=_t1;l=_t2;\
198: }
199:
200: #define DMAB(base,a1,a2,a3,u,l)\
201: {\
202: unsigned int _t1,_t2,_t3,_d;\
203: _t1=a1;_t2=a2;_t3=a3;_d=base;\
204: __asm\
205: {\
206: __asm mov eax,_t1\
207: __asm mul _t2\
208: __asm add eax,_t3\
209: __asm adc edx,0\
210: __asm div _d\
211: __asm mov _t1,eax\
212: __asm mov _t2,edx\
213: }\
214: u=_t1;l=_t2;\
215: }
216:
217: #define DMAR(a1,a2,a3,d,r)\
218: {\
219: unsigned int _t1,_t2,_t3,_d;\
220: _t1=a1;_t2=a2;_t3=a3,_d=d;\
221: __asm\
222: {\
223: __asm mov eax,_t1\
224: __asm mul _t2\
225: __asm add eax,_t3\
226: __asm adc edx,0\
227: __asm div _d\
228: __asm mov _t1,edx\
229: }\
230: r=_t1;\
231: }
232:
233: #define DSAB27(base,a1,a2,u,l)\
234: {\
235: unsigned int _t1,_t2,_d;\
236: _t1=a1;_t2=a2;_d=base;\
237: __asm\
238: {\
239: __asm mov edx,_t1\
240: __asm mov eax,_t2\
241: __asm mov ecx,edx\
242: __asm shl ecx,27\
243: __asm or eax,ecx\
244: __asm shr edx,5\
245: __asm div _d\
246: __asm mov _t1,eax\
247: __asm mov _t2,edx\
248: }\
249: u=_t1;l=_t2;\
250: }
251:
252: #define DM27(a1,a2,u,l)\
253: {\
254: unsigned int _t1,_t2;\
255: _t1=a1;_t2=a2;\
256: __asm\
257: {\
258: __asm mov eax,_t1\
259: __asm mul _t2\
260: __asm shl edx,5\
261: __asm mov ecx,eax\
262: __asm shr ecx,27\
263: __asm or edx,ecx\
264: __asm and eax,134217727\
265: __asm mov _t1,edx\
266: __asm mov _t2,eax\
267: }\
268: u=_t1;l=_t2;\
269: }
270:
271: #define DMA27(a1,a2,a3,u,l)\
272: {\
273: unsigned int _t1,_t2,_t3;\
274: _t1=a1;_t2=a2;_t3=a3;\
275: __asm\
276: {\
277: __asm mov eax,_t1\
278: __asm mul _t2\
279: __asm add eax,_t3\
280: __asm adc edx,0\
281: __asm shl edx,5\
282: __asm mov ecx,eax\
283: __asm shr ecx,27\
284: __asm or edx,ecx\
285: __asm and eax,134217727\
286: __asm mov _t1,edx\
287: __asm mov _t2,eax\
288: }\
289: u=_t1;l=_t2;\
290: }
291: #endif
292:
293: #if !defined(VISUAL) && defined(i386) && (defined(linux) || defined(__FreeBSD__) || defined(__NetBSD__))
294:
295: #if 0
296: #undef DMA
297: #define DMA(a1,a2,a3,u,l)\
1.5 noro 298: asm volatile("movl %0,%%eax" : : "g" (a1) : "ax");\
299: asm volatile("mull %0" : : "g" (a2) : "ax","dx");\
300: asm volatile("addl %0,%%eax" : : "g" (a3) : "ax" );\
1.1 noro 301: asm volatile("adcl $0,%%edx" : : : "dx" );\
1.5 noro 302: asm volatile("movl %%edx,%0" : "=g" (u) : : "ax","dx");\
303: asm volatile("movl %%eax,%0" : "=g" (l) : : "ax" );
1.1 noro 304: #endif
305:
306: #undef DM
1.7 ! noro 307: #undef DMA0
1.1 noro 308: #undef DMB
309: #undef DMAB
310: #undef DMAR
311: #undef DSAB
312: #undef DM27
313: #undef DMA27
314:
315: #define DM27(a1,a2,u,l)\
1.5 noro 316: asm volatile(" movl %2,%%eax; mull %3; shll $5,%%edx; movl %%eax,%%ecx; shrl $27,%%ecx; orl %%ecx,%%edx; andl $134217727,%%eax; movl %%edx,%0; movl %%eax,%1" :"=g"(u),"=g"(l) :"g"(a1),"g"(a2) :"ax","bx","cx","dx");
1.1 noro 317:
318: #define DMA27(a1,a2,a3,u,l)\
1.5 noro 319: asm volatile(" movl %2,%%eax; mull %3; addl %4,%%eax; adcl $0,%%edx; shll $5,%%edx; movl %%eax,%%ecx; shrl $27,%%ecx; orl %%ecx,%%edx; andl $134217727,%%eax; movl %%edx,%0; movl %%eax,%1" :"=g"(u),"=g"(l) :"g"(a1),"g"(a2),"g"(a3) :"ax","bx","cx","dx");
1.1 noro 320:
321: #define DSAB(base,a1,a2,u,l)\
1.5 noro 322: asm volatile(" movl %2,%%edx; movl %3,%%eax; divl %4; movl %%edx,%0; movl %%eax,%1" :"=g"(l),"=g"(u) :"g"(a1),"g"(a2),"g"(base) :"ax","dx");
1.1 noro 323:
324: #define DM(a1,a2,u,l)\
1.5 noro 325: asm volatile(" movl %2,%%eax; mull %3; movl %%edx,%0; movl %%eax,%1" :"=g"(u),"=g"(l) :"g"(a1),"g"(a2) :"ax","dx");
1.7 ! noro 326:
! 327: #define DMA0(a1,a2,a3,u,l)\
! 328: asm volatile("movl %2,%%eax; mull %3; addl %4,%%eax; adcl $0,%%edx; movl %%edx,%0; movl %%eax,%1" :"=g"(u), "=g"(l) :"g"(a1),"g"(a2),"g"(a3) :"ax","dx");
1.1 noro 329:
330: #define DMB(base,a1,a2,u,l)\
1.5 noro 331: asm volatile(" movl %2,%%eax;" mull %3;" divl %4;" movl %%edx,%0;" movl %%eax,%0" :"=g"(l),"=g"(u) :"g"(a1),"g"(a2),"g"(base) :"ax","dx");
1.1 noro 332:
333: #define DMAB(base,a1,a2,a3,u,l)\
1.5 noro 334: asm volatile("movl %2,%%eax; mull %3; addl %4,%%eax; adcl $0,%%edx; divl %5; movl %%edx,%0; movl %%eax,%1" :"=g"(l),"=g"(u) :"g"(a1),"g"(a2),"g"(a3),"g"(base) :"ax","dx");
1.1 noro 335:
336: #define DMAR(a1,a2,a3,d,r)\
1.5 noro 337: asm volatile("movl %1,%%eax; mull %2; addl %3,%%eax; adcl $0,%%edx; divl %4; movl %%edx,%0" :"=g"(r) :"g"(a1),"g"(a2),"g"(a3),"g"(d) :"ax","dx");
1.1 noro 338: #endif
339:
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