Annotation of OpenXM_contrib2/asir2018/include/inline.h, Revision 1.2
1.1 noro 1: /*
2: * Copyright (c) 1994-2000 FUJITSU LABORATORIES LIMITED
3: * All rights reserved.
4: *
5: * FUJITSU LABORATORIES LIMITED ("FLL") hereby grants you a limited,
6: * non-exclusive and royalty-free license to use, copy, modify and
7: * redistribute, solely for non-commercial and non-profit purposes, the
8: * computer program, "Risa/Asir" ("SOFTWARE"), subject to the terms and
9: * conditions of this Agreement. For the avoidance of doubt, you acquire
10: * only a limited right to use the SOFTWARE hereunder, and FLL or any
11: * third party developer retains all rights, including but not limited to
12: * copyrights, in and to the SOFTWARE.
13: *
14: * (1) FLL does not grant you a license in any way for commercial
15: * purposes. You may use the SOFTWARE only for non-commercial and
16: * non-profit purposes only, such as academic, research and internal
17: * business use.
18: * (2) The SOFTWARE is protected by the Copyright Law of Japan and
19: * international copyright treaties. If you make copies of the SOFTWARE,
20: * with or without modification, as permitted hereunder, you shall affix
21: * to all such copies of the SOFTWARE the above copyright notice.
22: * (3) An explicit reference to this SOFTWARE and its copyright owner
23: * shall be made on your publication or presentation in any form of the
24: * results obtained by use of the SOFTWARE.
25: * (4) In the event that you modify the SOFTWARE, you shall notify FLL by
26: * e-mail at risa-admin@sec.flab.fujitsu.co.jp of the detailed specification
27: * for such modification or the source code of the modified part of the
28: * SOFTWARE.
29: *
30: * THE SOFTWARE IS PROVIDED AS IS WITHOUT ANY WARRANTY OF ANY KIND. FLL
31: * MAKES ABSOLUTELY NO WARRANTIES, EXPRESSED, IMPLIED OR STATUTORY, AND
32: * EXPRESSLY DISCLAIMS ANY IMPLIED WARRANTY OF MERCHANTABILITY, FITNESS
33: * FOR A PARTICULAR PURPOSE OR NONINFRINGEMENT OF THIRD PARTIES'
34: * RIGHTS. NO FLL DEALER, AGENT, EMPLOYEES IS AUTHORIZED TO MAKE ANY
35: * MODIFICATIONS, EXTENSIONS, OR ADDITIONS TO THIS WARRANTY.
36: * UNDER NO CIRCUMSTANCES AND UNDER NO LEGAL THEORY, TORT, CONTRACT,
37: * OR OTHERWISE, SHALL FLL BE LIABLE TO YOU OR ANY OTHER PERSON FOR ANY
38: * DIRECT, INDIRECT, SPECIAL, INCIDENTAL, PUNITIVE OR CONSEQUENTIAL
39: * DAMAGES OF ANY CHARACTER, INCLUDING, WITHOUT LIMITATION, DAMAGES
40: * ARISING OUT OF OR RELATING TO THE SOFTWARE OR THIS AGREEMENT, DAMAGES
41: * FOR LOSS OF GOODWILL, WORK STOPPAGE, OR LOSS OF DATA, OR FOR ANY
42: * DAMAGES, EVEN IF FLL SHALL HAVE BEEN INFORMED OF THE POSSIBILITY OF
43: * SUCH DAMAGES, OR FOR ANY CLAIM BY ANY OTHER PARTY. EVEN IF A PART
44: * OF THE SOFTWARE HAS BEEN DEVELOPED BY A THIRD PARTY, THE THIRD PARTY
45: * DEVELOPER SHALL HAVE NO LIABILITY IN CONNECTION WITH THE USE,
46: * PERFORMANCE OR NON-PERFORMANCE OF THE SOFTWARE.
47: *
1.2 ! noro 48: * $OpenXM: OpenXM_contrib2/asir2018/include/inline.h,v 1.1 2018/09/19 06:00:58 noro Exp $
1.1 noro 49: */
50: #define DMB(base,a1,a2,u,l) (l)=dmb(base,a1,a2,&(u));
51: #define DMAB(base,a1,a2,a3,u,l) (l)=dmab(base,a1,a2,a3,&(u));
52: #define DMAR(a1,a2,a3,d,r) (r)=dmar(a1,a2,a3,d);
53: #define DM27(a1,a2,u,l) (l)=dm_27(a1,a2,&(u));
54: #define DMA27(a1,a2,a3,u,l) (l)=dma_27(a1,a2,a3,&(u));
55: #define DSAB27(base,a1,a2,u,l) (l)=dmab(base,a1,BASE27,a2,&(u));
56:
1.2 ! noro 57: #if defined(__GNUC__) || defined(__INTEL_COMPILER) || defined(__alpha) || defined(mips) || defined(_IBMR2) || defined(_WIN64)
1.1 noro 58: #define DM(a1,a2,u,l)\
59: {UL _t;\
60: _t=(UL)(a1)*(UL)(a2);\
61: (u)=(unsigned int)(_t>>BSH);\
62: (l)=(unsigned int)(_t&BMASK);}
63:
64: #define DMA(a1,a2,a3,u,l)\
65: {UL _t;\
66: _t=(UL)(a1)*(UL)(a2)+(UL)(a3);\
67: (u)=(unsigned int)(_t>>BSH);\
68: (l)=(unsigned int)(_t&BMASK);}
69:
70: #define DMA2(a1,a2,a3,a4,u,l)\
71: {UL _t;\
72: _t=(UL)(a1)*(UL)(a2)+(UL)(a3)+(UL)(a4);\
73: (u)=(unsigned int)(_t>>BSH);\
74: (l)=(unsigned int)(_t&BMASK);}
75:
76: #define DSAB(base,a1,a2,u,l)\
77: {UL _t;\
78: _t=(((UL)(a1))<<BSH)|((UL)(a2));\
79: (u)=(unsigned int)(_t/((UL)(base)));\
80: (l)=(unsigned int)(_t-((UL)(base)*(UL)(u)));}
81: #else
82: #define DM(a1,a2,u,l) (l)=dm(a1,a2,&(u));
83: #define DMA(a1,a2,a3,u,l) (l)=dma(a1,a2,a3,&(u));
84: #define DMA2(a1,a2,a3,a4,u,l) (l)=dma2(a1,a2,a3,a4,&(u));
85: #define DSAB(base,a1,a2,u,l) (l)=dsab(base,a1,a2,&(u));
86: #endif
87:
88: #define DQR(a,b,q,r)\
89: (q)=(a)/(b);\
90: (r)=(a)-(b)*(q);
91:
92: #if defined(sparc)
93: #undef DSAB
94: #undef DSAB27
95:
96: #define DSAB(base,a1,a2,u,l)\
97: {unsigned int _t;\
98: asm volatile("wr %0,%%g0,%%y" : : "r"(a1) );\
99: asm volatile("udiv %1,%2,%0" :"=r"(_t): "r"(a2),"r"(base) );\
100: (l)=(unsigned int)(a2)-(unsigned int)(_t)*(unsigned int)(base);\
101: (u)=(_t);}
102:
103: #define DSAB27(base,a1,a2,u,l) (l)=dsab_27(base,a1,a2,&(u));
104: #endif
105:
106: #if defined(_M_IX86) && !defined(__MINGW32__)
107:
108: #undef DM
109: #undef DMA
110: #undef DMA2
111: #undef DMB
112: #undef DMAB
113: #undef DMAR
114: #undef DSAB
115: #undef DM27
116: #undef DMA27
117: #undef DSAB27
118:
119: #define DSAB(base,a1,a2,u,l)\
120: {\
121: unsigned int _t1,_t2,_d;\
122: _t1=a1;_t2=a2;_d=base;\
123: __asm\
124: {\
125: __asm mov edx,_t1\
126: __asm mov eax,_t2\
127: __asm div _d\
128: __asm mov _t1,eax\
129: __asm mov _t2,edx\
130: }\
131: u=_t1;l=_t2;\
132: }
133:
134: #define DM(a1,a2,u,l)\
135: {\
136: unsigned int _t1,_t2;\
137: _t1=a1;_t2=a2;\
138: __asm\
139: {\
140: __asm mov eax,_t1\
141: __asm mul _t2\
142: __asm mov _t1,edx\
143: __asm mov _t2,eax\
144: }\
145: u=_t1;l=_t2;\
146: }
147:
148: #define DMA(a1,a2,a3,u,l)\
149: {\
150: unsigned int _t1,_t2,_t3;\
151: _t1=a1;_t2=a2;_t3=a3;\
152: __asm\
153: {\
154: __asm mov eax,_t1\
155: __asm mul _t2\
156: __asm add eax,_t3\
157: __asm adc edx,0\
158: __asm mov _t1,edx\
159: __asm mov _t2,eax\
160: }\
161: u=_t1;l=_t2;\
162: }
163:
164: #define DMA2(a1,a2,a3,a4,u,l)\
165: {\
166: unsigned int _t1,_t2,_t3,_t4;\
167: _t1=a1;_t2=a2;_t3=a3;_t4=a4;\
168: __asm\
169: {\
170: __asm mov eax,_t1\
171: __asm mul _t2\
172: __asm add eax,_t3\
173: __asm adc edx,0\
174: __asm add eax,_t4\
175: __asm adc edx,0\
176: __asm mov _t1,edx\
177: __asm mov _t2,eax\
178: }\
179: u=_t1;l=_t2;\
180: }
181:
182: #define DMB(base,a1,a2,u,l)\
183: {\
184: unsigned int _t1,_t2,_d;\
185: _t1=a1;_t2=a2;_d=base;\
186: __asm\
187: {\
188: __asm mov eax,_t1\
189: __asm mul _t2\
190: __asm div _d\
191: __asm mov _t1,eax\
192: __asm mov _t2,edx\
193: }\
194: u=_t1;l=_t2;\
195: }
196:
197: #define DMAB(base,a1,a2,a3,u,l)\
198: {\
199: unsigned int _t1,_t2,_t3,_d;\
200: _t1=a1;_t2=a2;_t3=a3;_d=base;\
201: __asm\
202: {\
203: __asm mov eax,_t1\
204: __asm mul _t2\
205: __asm add eax,_t3\
206: __asm adc edx,0\
207: __asm div _d\
208: __asm mov _t1,eax\
209: __asm mov _t2,edx\
210: }\
211: u=_t1;l=_t2;\
212: }
213:
214: #define DMAR(a1,a2,a3,d,r)\
215: {\
216: unsigned int _t1,_t2,_t3,_d;\
217: _t1=a1;_t2=a2;_t3=a3,_d=d;\
218: __asm\
219: {\
220: __asm mov eax,_t1\
221: __asm mul _t2\
222: __asm add eax,_t3\
223: __asm adc edx,0\
224: __asm div _d\
225: __asm mov _t1,edx\
226: }\
227: r=_t1;\
228: }
229:
230: #define DSAB27(base,a1,a2,u,l)\
231: {\
232: unsigned int _t1,_t2,_d;\
233: _t1=a1;_t2=a2;_d=base;\
234: __asm\
235: {\
236: __asm mov edx,_t1\
237: __asm mov eax,_t2\
238: __asm mov ecx,edx\
239: __asm shl ecx,27\
240: __asm or eax,ecx\
241: __asm shr edx,5\
242: __asm div _d\
243: __asm mov _t1,eax\
244: __asm mov _t2,edx\
245: }\
246: u=_t1;l=_t2;\
247: }
248:
249: #define DM27(a1,a2,u,l)\
250: {\
251: unsigned int _t1,_t2;\
252: _t1=a1;_t2=a2;\
253: __asm\
254: {\
255: __asm mov eax,_t1\
256: __asm mul _t2\
257: __asm shl edx,5\
258: __asm mov ecx,eax\
259: __asm shr ecx,27\
260: __asm or edx,ecx\
261: __asm and eax,134217727\
262: __asm mov _t1,edx\
263: __asm mov _t2,eax\
264: }\
265: u=_t1;l=_t2;\
266: }
267:
268: #define DMA27(a1,a2,a3,u,l)\
269: {\
270: unsigned int _t1,_t2,_t3;\
271: _t1=a1;_t2=a2;_t3=a3;\
272: __asm\
273: {\
274: __asm mov eax,_t1\
275: __asm mul _t2\
276: __asm add eax,_t3\
277: __asm adc edx,0\
278: __asm shl edx,5\
279: __asm mov ecx,eax\
280: __asm shr ecx,27\
281: __asm or edx,ecx\
282: __asm and eax,134217727\
283: __asm mov _t1,edx\
284: __asm mov _t2,eax\
285: }\
286: u=_t1;l=_t2;\
287: }
288: #endif
289:
290: #if !defined(VISUAL) && defined(i386) && (defined(linux) || defined(__FreeBSD__) || defined(__NetBSD__) || defined(__CYGWIN__) || defined(__DARWIN__))
291:
292: #if 0
293: #undef DMA
294: #define DMA(a1,a2,a3,u,l)\
295: asm volatile("movl %0,%%eax" : : "g" (a1) : "ax");\
296: asm volatile("mull %0" : : "g" (a2) : "ax","dx");\
297: asm volatile("addl %0,%%eax" : : "g" (a3) : "ax" );\
298: asm volatile("adcl $0,%%edx" : : : "dx" );\
299: asm volatile("movl %%edx,%0" : "=g" (u) : : "ax","dx");\
300: asm volatile("movl %%eax,%0" : "=g" (l) : : "ax" );
301: #endif
302:
303: #undef DM
304: #undef DMA
305: #undef DMB
306: #undef DMAB
307: #undef DMAR
308: #undef DSAB
309: #undef DM27
310: #undef DMA27
311:
312: #define DM27(a1,a2,u,l)\
313: asm volatile(" movl %2,%%eax; mull %3; shll $5,%%edx; movl %%eax,%%ecx; shrl $27,%%ecx; orl %%ecx,%%edx; andl $134217727,%%eax; movl %%edx,%0; movl %%eax,%1" :"=g"(u),"=g"(l) :"g"(a1),"g"(a2) :"ax","bx","cx","dx");
314:
315: #define DMA27(a1,a2,a3,u,l)\
316: asm volatile(" movl %2,%%eax; mull %3; addl %4,%%eax; adcl $0,%%edx; shll $5,%%edx; movl %%eax,%%ecx; shrl $27,%%ecx; orl %%ecx,%%edx; andl $134217727,%%eax; movl %%edx,%0; movl %%eax,%1" :"=g"(u),"=g"(l) :"g"(a1),"g"(a2),"g"(a3) :"ax","bx","cx","dx");
317:
318: #define DSAB(base,a1,a2,u,l)\
319: asm volatile(" movl %2,%%edx; movl %3,%%eax; divl %4; movl %%edx,%0; movl %%eax,%1" :"=g"(l),"=g"(u) :"g"(a1),"g"(a2),"g"(base) :"ax","dx");
320:
321: #define DM(a1,a2,u,l)\
322: asm volatile(" movl %2,%%eax; mull %3; movl %%edx,%0; movl %%eax,%1" :"=g"(u),"=g"(l) :"g"(a1),"g"(a2) :"ax","dx");
323:
324: #define DMA(a1,a2,a3,u,l)\
325: asm volatile("movl %2,%%eax; mull %3; addl %4,%%eax; adcl $0,%%edx; movl %%edx,%0; movl %%eax,%1" :"=g"(u), "=g"(l) :"g"(a1),"g"(a2),"g"(a3) :"ax","dx");
326:
327: #define DMB(base,a1,a2,u,l)\
328: asm volatile(" movl %2,%%eax;" mull %3;" divl %4;" movl %%edx,%0;" movl %%eax,%0" :"=g"(l),"=g"(u) :"g"(a1),"g"(a2),"g"(base) :"ax","dx");
329:
330: #define DMAB(base,a1,a2,a3,u,l)\
331: asm volatile("movl %2,%%eax; mull %3; addl %4,%%eax; adcl $0,%%edx; divl %5; movl %%edx,%0; movl %%eax,%1" :"=g"(l),"=g"(u) :"g"(a1),"g"(a2),"g"(a3),"g"(base) :"ax","dx");
332:
333: #define DMAR(a1,a2,a3,d,r)\
334: asm volatile("movl %1,%%eax; mull %2; addl %3,%%eax; adcl $0,%%edx; divl %4; movl %%edx,%0" :"=g"(r) :"g"(a1),"g"(a2),"g"(a3),"g"(d) :"ax","dx");
335: #endif
336:
FreeBSD-CVSweb <freebsd-cvsweb@FreeBSD.org>
![[BACK]](/icons/cvsweb/back.gif){kind=icon}
Return to inline.h CVS log ![[TXT]](/icons/cvsweb/text.gif){kind=icon}
![[DIR]](/icons/cvsweb/dir.gif){kind=icon}
Up to [local] / OpenXM_contrib2 / asir2018 / include