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This directory contains mpn functions for 64-bit PA-RISC 2.0.

PIPELINE SUMMARY

The PA8x00 processors have an orthogonal 4-way out-of-order pipeline.  Each
cycle two ALU operations and two MEM operations can issue, but just one of the
MEM operations may be a store.  The two ALU operations can be almost any
combination of non-memory operations.  Unlike every other processor, integer
and fp operations are completely equal here; they both count as just ALU
operations.

Unfortunately, some operations cause hickups in the pipeline.  Combining
carry-consuming operations like ADD,DC with operations that does not set carry
like ADD,L cause long delays.  Skip operations also seem to cause hickups.  If
several ADD,DC are issued consecutively, or if plain carry-generating ADD feed
ADD,DC, stalling does not occur.  We can effectively issue two ADD,DC
operations/cycle.

Latency scheduling is not as important as making sure to have a mix of ALU and
MEM operations, but for full pipeline utilization, it is still a good idea to
do some amount of latency scheduling.

Like for all other processors, RAW memory scheduling is critically important.
Since integer multiplication takes place in the floating-point unit, the GMP
code needs to handle this problem frequently.

STATUS

* mpn_lshift and mpn_rshift run at 1.5 cycles/limb on PA8000 and at 1.0
  cycles/limb on PA8500.  With latency scheduling, the numbers could be
  improved to 1.0 cycles/limb for all PA8x00 chips.

* mpn_add_n and mpn_sub_n run at 2.0 cycles/limb on PA8000 and at about 1.9
  cycles/limb on PA8500.  With latency scheduling, this could be improved to
  1.5 cycles/limb.

* The mpn_addmul_1 run at 6.25 cycles/limb.  The current code uses ADD,DC for
  adjacent limbs, and relies heavily on reordering.

* Both mpn_mul_1 and mpn_submul_1 run at around 11 cycles/limb.  There is
  obviously room for improving these along the lines of mpn_addmul_1.